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Séminaires et colloques
Séminaire des Doctorants 2014: J. Proudom, M. Zeloufi
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Europe/Paris
Grand amphi
Grand amphi
Description
J. Proudom: Characterizing New Physics with Polarized Beams at High-Energy Hadron Colliders
Abstract: If new physics has to be discovered in the forthcoming years, the ultimate goal of the high-energy physics program will consist of fully characterizing the newly-discovered degrees of freedom in terms of properties such as their masses, spins and couplings. In this talk, I will show how the availability of polarized beams at high-energy proton-proton colliders could yield a unique discriminating power between different beyond the Standard Model scenarios giving the same final-state signature, and how polarized beams could be help us to obtain information on the parameters of the hypothetical new physics sector of the theory. I will discuss as an illustrative example the case of a particular class of models leading to monotop production, and explain how these models could be distinguished by means of single- and double-spin asymmetries in polarized collisions at a Large Hadron Collider operating at a center of-mass energy of 14 TeV and at the recently proposed Future Circular Collider.
M. Zeloufi: Design of an innovative analog to digital converter for the ATLAS/LARG electronics readout in LHC high luminosity configuration
Abstract: Particle detectors, like the liquid argon calorimeter for ATLAS experiment at the Large Hadron Collider (LHC), create an enormous dataflow. To read and process these data it is necessary to use a low noise and high dynamic range electronic system that precisely measures the signal from the detectors.
For the High Luminosity version for LHC, one might deal with new challenges according to the power dissipation while the speed and the dynamic range should remain constant. One solution is to fully integrate the read-out electronics from the preamplifier to the Analog to digital converter. One key element is then the integration of the (ADC) in a very aggressive and rad hard CMOS process. Beside the power dissipation constraint, the other main features are: a high sampling rate (40MS/s), large dynamic range (12 to 14 bits), and even low latency (below 100ns) for the trigger flow. In this talk, a new ADC architecture will be presented based on a successive approximations configuration.
Abstract: If new physics has to be discovered in the forthcoming years, the ultimate goal of the high-energy physics program will consist of fully characterizing the newly-discovered degrees of freedom in terms of properties such as their masses, spins and couplings. In this talk, I will show how the availability of polarized beams at high-energy proton-proton colliders could yield a unique discriminating power between different beyond the Standard Model scenarios giving the same final-state signature, and how polarized beams could be help us to obtain information on the parameters of the hypothetical new physics sector of the theory. I will discuss as an illustrative example the case of a particular class of models leading to monotop production, and explain how these models could be distinguished by means of single- and double-spin asymmetries in polarized collisions at a Large Hadron Collider operating at a center of-mass energy of 14 TeV and at the recently proposed Future Circular Collider.
M. Zeloufi: Design of an innovative analog to digital converter for the ATLAS/LARG electronics readout in LHC high luminosity configuration
Abstract: Particle detectors, like the liquid argon calorimeter for ATLAS experiment at the Large Hadron Collider (LHC), create an enormous dataflow. To read and process these data it is necessary to use a low noise and high dynamic range electronic system that precisely measures the signal from the detectors.
For the High Luminosity version for LHC, one might deal with new challenges according to the power dissipation while the speed and the dynamic range should remain constant. One solution is to fully integrate the read-out electronics from the preamplifier to the Analog to digital converter. One key element is then the integration of the (ADC) in a very aggressive and rad hard CMOS process. Beside the power dissipation constraint, the other main features are: a high sampling rate (40MS/s), large dynamic range (12 to 14 bits), and even low latency (below 100ns) for the trigger flow. In this talk, a new ADC architecture will be presented based on a successive approximations configuration.
